Bumpless build-up layer package with a pre-stacked microelectronic devices

ABSTRACT

The present disclosure relates to the field of integrated circuit package design and, more particularly, to packages using a bumpless build-up layer (BBUL) designs. Embodiments of the present description relate to the field of fabricating microelectronic packages, wherein a first microelectronic device having through-silicon vias may be stacked with a second microelectronic device and used in a bumpless build-up layer package.

CLAIM OF PRIORITY

This is a Continuation of application Ser. No. 15/170,833 filed Jun. 1,2016, which is a Continuation of application Ser. No. 14/269,318 filedMay 5, 2014 now U.S. Pat. No. 9,362,253 issued Sep. 28, 2014, which is aContinuation of application Ser. No. 12/868,816 filed Aug. 26, 2010 nowU.S. Pat. No. 8,754,516 issued Jun. 17, 2014, which are herebyincorporated by reference.

BACKGROUND

Embodiments of the present description generally relate to the field ofmicroelectronic device package designs and, more particularly, to amicroelectronic device package having pre-stacked microelectronicdevices in a bumpless build-up layer (BBUL) design.

BRIEF DESCRIPTION OF THE DRAWINGS

The subject matter of the present disclosure is particularly pointed outand distinctly claimed in the concluding portion of the specification.The foregoing and other features of the present disclosure will becomemore fully apparent from the following description and appended claims,taken in conjunction with the accompanying drawings. It is understoodthat the accompanying drawings depict only several embodiments inaccordance with the present disclosure and are, therefore, not to beconsidered limiting of its scope. The disclosure will be described withadditional specificity and detail through use of the accompanyingdrawings, such that the advantages of the present disclosure can be morereadily ascertained, in which:

FIGS. 1-9 illustrate side cross-sectional views of a process of forminga microelectronic device package having pre-stacked microelectronicdevices in a bumpless build-up layer design.

FIG. 10 illustrates a side cross-sectional view of another embodiment ofa microelectronic device package having pre-stacked microelectronicdevices in a bumpless build-up layer design.

DETAILED DESCRIPTION

In the following detailed description, reference is made to theaccompanying drawings that show, by way of illustration, specificembodiments in which the claimed subject matter may be practiced. Theseembodiments are described in sufficient detail to enable those skilledin the art to practice the subject matter. It is to be understood thatthe various embodiments, although different, are not necessarilymutually exclusive. For example, a particular feature, structure, orcharacteristic described herein, in connection with one embodiment, maybe implemented within other embodiments without departing from thespirit and scope of the claimed subject matter. In addition, it is to beunderstood that the location or arrangement of individual elementswithin each disclosed embodiment may be modified without departing fromthe spirit and scope of the claimed subject matter. The followingdetailed description is, therefore, not to be taken in a limiting sense,and the scope of the subject matter is defined only by the appendedclaims, appropriately interpreted, along with the full range ofequivalents to which the appended claims are entitled. In the drawings,like numerals refer to the same or similar elements or functionalitythroughout the several views, and that elements depicted therein are notnecessarily to scale with one another, rather individual elements may beenlarged or reduced in order to more easily comprehend the elements inthe context of the present description.

Embodiments of the present description relate to the field offabricating microelectronic packages, wherein a first microelectronicdevice having through-silicon vias may be stacked with a secondmicroelectronic device and used in a bumpless build-up layer package.

FIGS. 1-8 illustrate cross-sectional views of an embodiment of a processof forming a bumpless build-up layer coreless (BBUL-C) microelectronicpackage. As shown in FIG. 1, a first microelectronic device 102 may beprovided, wherein the first microelectronic device 102 includes anactive surface 104, an opposing back surface 106 that is substantiallyparallel to the first microelectronic device active surface 104, and atleast one side 108 extending from the first microelectronic deviceactive surface 104 to the first microelectronic device back surface 106.The first microelectronic device 102 may have an active portion 105proximate the first microelectronic device active surface 104 and asubstrate portion 107 extending from the first microelectronic deviceactive portion 105 to the first microelectronic device back surface 106.As will be understood to those skilled in the art, the firstmicroelectronic device active portion 105 comprises the integratedcircuitry and interconnections (not shown) of the first microelectronicdevice 102. The first microelectronic device 102 may be any appropriateintegrated circuit device including but not limited to a microprocessor(single or multi-core), a memory device, a chipset, a graphics device,an application specific integrated circuit, or the like. In oneembodiment, the first microelectronic device 102 is a microprocessor.

The first microelectronic device 102 may have at least one conductivevia extending through the first microelectronic device substrate portion107 from the first microelectronic device back surface 106 to the firstmicroelectronic device active portion 105. Such a conductive viaconfiguration is known as a through-silicon via 112. The firstmicroelectronic device through-silicon via(s) 112 may be in electricalcommunication with the integrated circuitry (not shown) in the firstmicroelectronic device active portion 105. Each first microelectronicdevice through-silicon via 112 may have a contact land 116 on the firstmicroelectronic device back surface 106. Although the firstmicroelectronic device back surface contact lands are shown directlyadjacent the first microelectronic device through-silicon vias 112, itis understood that they may be positioned at any appropriate location onthe first microelectronic die back surface with conductive tracesforming electrical contact therebetween. The first microelectronicdevice through-silicon vias 112 and the first microelectronic deviceback surface contact lands 116 may be fabricated by any technique knownin the art, including, but not limited to drilling (laser and ion),lithography, plating, and deposition, and may be made of any appropriateconductive material, including but not limited to copper, aluminum,silver, gold, or alloys thereof.

As shown in FIG. 2, a second microelectronic device 122 may be alignedwith the first microelectronic device 102. The second microelectronicdevice 122 may have an active surface 124, a back surface 126 that issubstantially parallel to the second microelectronic device activesurface 124, and at least one side 128 extending from the secondmicroelectronic device active surface 124 to the second microelectronicdevice back surface 126. The second microelectronic device 122 mayfurther include at least one contact land 132 adjacent themicroelectronic device active surface 124, wherein the secondmicroelectronic device contact lands 132 may be connected to integratedcircuits (not shown) within the second microelectronic device 122. Thesecond microelectronic device 122 may be any appropriate integratedcircuit device including but not limited to a microprocessor (single ormulti-core), a memory device, a chipset, a graphics device, anapplication specific integrated circuit, or the like. In one embodiment,the second microelectronic device 122 is a memory device. The secondmicroelectronic device contact lands 132 may be any appropriateconductive material, including but not limited to copper, aluminum,silver, gold, or alloys thereof.

As further shown in FIG. 2, the second microelectronic device 122 may beattached to the first microelectronic device 102 through a plurality ofinterconnects 136 (shown as solder balls) connecting the secondmicroelectronic device contact lands 132 to the first microelectronicdevice back surface contact lands 116, thereby forming a stackedstructure 140. An underfill material 138, such as an epoxy material, maybe disposed between the first microelectronic device back surface 106and the second microelectronic device active surface 124, and around theplurality of interconnects 136. The underfill material 138 may enhancethe structural integrity of the stacked structure 140.

As shown in FIG. 3, the second microelectronic device back surface 126may be attached to a carrier 150, such as with a DBF (die backside film)or an adhesive (not shown), as known to those skilled in the art. Anencapsulation material 152 may be disposed adjacent the secondmicroelectronic device side(s) 128, the first microelectronic side(s)108, and over the first microelectronic device active surface 104including the first microelectronic device active surface contactland(s) 114, thereby forming a front surface 154 of the encapsulationmaterial 152, as shown in FIG. 4. The placement of the secondmicroelectronic device back surface 126 on the carrier 150 may result ina back surface 156 of the encapsulation material 152 being formedsubstantially planar with the second microelectronic device back surface126, thereby forming substrate 160.

The encapsulation material 152 may be disposed by any process known inthe art, including a laminated process, as will be understood to thoseskilled in the art, and may be any appropriate dielectric material,including, but not limited to silica-filled epoxies, such as areavailable from Ajinomoto Fine-Techno Co., Inc., 1-2 Suzuki-cho,Kawasaki-ku, Kawasaki-shi, 210-0801, Japan (Ajinomoto GX13, AjinomotoGX92, and the like).

Vias 162 may be formed through the encapsulation material front surface154 to expose at least a portion of each first microelectronic deviceactive surface contact land 114, as shown in FIG. 5. The vias 162 ofFIG. 5 may be formed by any technique known in the art, including butnot limited to laser drilling, ion drilling, and lithography, as will beunderstood to those skilled in the art. A patterning and plating processmay be used to fill the vias 162 to form conductive vias 164 and tosimultaneously form first layer conductive traces 172, as will beunderstood by those skilled in the art, as shown in FIG. 6.

As shown in FIG. 7, a build-up layer 170 may be formed on theencapsulation material front surface 154. The build-up layer 170 maycomprise a plurality of dielectric layers with conductive traces formedon each dielectric layer with conductive vias extending through eachdielectric layer to connect the conductive traces on different layers.Referring to FIG. 7, the build-up layer 170 may comprise the first layerconductive traces 172 with a dielectric layer 174 formed adjacent thefirst layer conductive traces 172 and the encapsulation material frontsurface 154. At least one trace-to-trace conductive via 176 may extendthrough the dielectric layer 174 to connect at least one first layerconductive trace 172 to a second layer conductive trace 178. A solderresist material 180 may be patterned on the dielectric layer 174 andsecond layer conductive traces 178 having at least one opening 182exposing at least a portion of the second layer conductive traces 178.

As shown in FIG. 8, at least one external interconnect 184 may be formedon the second layer conductive traces 178 through patterned openings 182in the solder resist material 180. The external interconnects 184 may bea solder material and may be used to connect the build-up layer 170 toexternal components (not shown).

It is understood that although only one dielectric layer and twoconductive trace layers are shown, the build-up layer 170 may be anyappropriate number of dielectric layers and conductive trace layers. Thedielectric layer(s), such as the dielectric layer 174, may be formed byany technique known in the art and may be any appropriate dielectricmaterial. The conductive trace layers, such as first layer conductivetraces 172 and the second layer conductive traces 178, and theconductive vias 176, may be fabricated by any technique known in theart, including but not limited to plating and lithography, and may bemade of any appropriate conductive material, including but not limitedto copper, aluminum, silver, gold, or alloys thereof.

The carrier 150 may be removed, resulting in a microelectronic package190, as shown in FIG. 9. The stacking and encapsulation of the firstmicroelectronic device 102 and the second microelectronic device 122results in the microelectronic package 190 being sufficiently thickenough to prevent warpage in the microelectronic package 190, which mayresult in a reduction in yield losses from solder ball bridging and/ornon-contact opens, as will be understood to those skilled in the art.

Another embodiment of a microelectronic package 192 is shown in FIG. 10.In this embodiment, the first microelectronic device active surface 104may be in electrical communication with the second microelectronicdevice active surface 124 through the interconnects 136 extendingbetween the first microelectronic device active surface contact land 114and the second microelectronic device contact lands 132. The build-uplayer 170 may be formed proximate on the first microelectronic deviceback surface and may be in electrical communication with the firstmicroelectronic device through-silicon vias 112.

It is also understood that the subject matter of the present descriptionis not necessarily limited to specific applications illustrated in FIGS.1-10. The subject matter may be applied to other stacked deviceapplications. Furthermore, the subject matter may also be used in anyappropriate application outside of the microelectronic devicefabrication field. Furthermore, the subject matter of the presentdescription may be a part of a larger bumpless build-up package, it mayinclude multiple stacked microelectronic dice, it may be formed at awafer level, or any number of appropriate variations, as will beunderstood to those skilled in the art.

The detailed description has described various embodiments of thedevices and/or processes through the use of illustrations, blockdiagrams, flowcharts, and/or examples. Insofar as such illustrations,block diagrams, flowcharts, and/or examples contain one or morefunctions and/or operations, it will be understood by those skilled inthe art that each function and/or operation within each illustration,block diagram, flowchart, and/or example can be implemented,individually and/or collectively, by a wide range of hardware, software,firmware, or virtually any combination thereof.

The described subject matter sometimes illustrates different componentscontained within, or connected with, different other components. It isunderstood that such illustrations are merely exemplary, and that manyalternate structures can be implemented to achieve the samefunctionality. In a conceptual sense, any arrangement of components toachieve the same functionality is effectively “associated” such that thedesired functionality is achieved. Thus, any two components hereincombined to achieve a particular functionality can be seen as“associated with” each other such that the desired functionality isachieved, irrespective of structures or intermediate components.Likewise, any two components so associated can also be viewed as being“operably connected”, or “operably coupled”, to each other to achievethe desired functionality, and any two components capable of being soassociated can also be viewed as being “operably couplable”, to eachother to achieve the desired functionality. Specific examples ofoperably couplable include but are not limited to physically mateableand/or physically interacting components and/or wirelessly interactableand/or wirelessly interacting components and/or logically interactingand/or logically interactable components.

It will be understood by those skilled in the art that terms usedherein, and especially in the appended claims are generally intended as“open” terms. In general, the terms “including” or “includes” should beinterpreted as “including but not limited to” or “includes but is notlimited to”, respectively. Additionally, the term “having” should beinterpreted as “having at least”.

The use of plural and/or singular terms within the detailed descriptioncan be translated from the plural to the singular and/or from thesingular to the plural as is appropriate to the context and/or theapplication.

It will be further understood by those skilled in the art that if anindication of the number of elements is used in a claim, the intent forthe claim to be so limited will be explicitly recited in the claim, andin the absence of such recitation no such intent is present.Additionally, if a specific number of an introduced claim recitation isexplicitly recited, those skilled in the art will recognize that suchrecitation should typically be interpreted to mean “at least” therecited number.

The use of the terms “an embodiment,” “one embodiment,” “someembodiments,” “another embodiment,” or “other embodiments” in thespecification may mean that a particular feature, structure, orcharacteristic described in connection with one or more embodiments maybe included in at least some embodiments, but not necessarily in allembodiments. The various uses of the terms “an embodiment,” “oneembodiment,” “another embodiment,” or “other embodiments” in thedetailed description are not necessarily all referring to the sameembodiments.

While certain exemplary techniques have been described and shown hereinusing various methods and systems, it should be understood by thoseskilled in the art that various other modifications may be made, andequivalents may be substituted, without departing from claimed subjectmatter or spirit thereof. Additionally, many modifications may be madeto adapt a particular situation to the teachings of claimed subjectmatter without departing from the central concept described herein.Therefore, it is intended that claimed subject matter not be limited tothe particular examples disclosed, but that such claimed subject matteralso may include all implementations falling within the scope of theappended claims, and equivalents thereof.

What is claimed is:
 1. A microelectronic package, comprising: asubstrate; a plurality of stacked microelectronic dies above thesubstrate, the plurality of stacked microelectronic dies having abottommost microelectronic die proximate the substrate, and a nextbottommost microelectronic die above the bottommost microelectronic die,wherein the bottommost microelectronic die has a plurality of front sidelands on an active portion facing the substrate and a plurality ofbackside lands facing the next bottommost microelectronic die with aplurality of through silicon vias (TSVs) electrically coupling thebackside lands and the front side lands of the bottommostmicroelectronic die, wherein the next bottommost microelectronic die hasa plurality of front side lands facing the bottommost microelectronicdie, wherein the plurality of backside lands of the bottommostmicroelectronic die is directly coupled to the plurality of front sidelands of the next bottommost microelectronic die by a solder layer, andwherein the plurality of front side lands of the bottommostmicroelectronic die electrically couples the bottommost microelectronicdie to the substrate, wherein the TSVs of the bottommost microelectronicdie are in direct contact with the backside lands of the bottommostmicroelectronic die but are not in direct contact with the front sidelands of the bottommost microelectronic die; an underfill material layerbetween the bottommost microelectronic die and the next bottommostmicroelectronic die; and an encapsulation material over the substrateand laterally adjacent to the bottommost microelectronic die, the nextbottommost microelectronic die and the underfill material layer, whereinthe encapsulation material is separate and distinct from the underfillmaterial layer
 2. The microelectronic package of claim 1, wherein theencapsulation material has an uppermost surface substantially co-planarwith an uppermost surface of an uppermost microelectronic die of theplurality of stacked microelectronic dies.
 3. The microelectronicpackage of claim 2, wherein the next bottommost microelectronic die isthe uppermost microelectronic die of the plurality of stackedmicroelectronic dies, and wherein the uppermost surface of theencapsulation material is substantially co-planar with an uppermostsurface of the next bottommost microelectronic die distal from thesubstrate.
 4. The microelectronic package of claim 1, wherein theencapsulation material comprises a silica-filled epoxy.
 5. A method offabricating a microelectronic package, the method comprising: forming aplurality of stacked dies comprising at least a first die and a seconddie above a carrier, wherein the first die has a plurality of front sidelands and has a plurality of backside lands facing the second die with aplurality of through silicon vias (TSVs) electrically coupling thebackside lands and the front side lands of the first die, wherein thesecond die has a plurality of front side lands facing the first die,wherein the plurality of backside lands of the first die is directlycoupled to the plurality of front side lands of the second die by asolder layer; subsequent to forming the plurality of stacked dies,forming an underfill material layer between the first die and the seconddie; subsequent to forming the underfill material layer, forming anencapsulation material over the carrier and laterally adjacent to thefirst die, the second die and the underfill material layer; subsequentto forming the encapsulation material, forming a substrate over theencapsulation material, wherein the plurality of front side lands of thefirst die electrically couples the first die to the substrate; andremoving the carrier.
 6. The method of claim 5, wherein forming theencapsulation material comprises forming a silica-filled epoxy.
 7. Themethod of claim 5, wherein the encapsulation material has a lowermostsurface substantially co-planar with a lowermost surface of a lowermostdie of the plurality of stacked dies.
 8. The method of claim 7, whereinthe second die is the lowermost die of the plurality of stacked dies,and wherein the lowermost surface of the encapsulation material issubstantially co-planar with lowermost surface of the second dieproximate the carrier.
 9. The method of claim 5, wherein the TSVs of thefirst die are in direct contact with the backside lands of thebottommost die but are not in direct contact with the front side landsof the bottommost die.
 10. A microelectronic package, comprising: asubstrate; a plurality of stacked dies above the substrate, theplurality of stacked dies having a bottommost die proximate thesubstrate, and a next bottommost die above the bottommost die, whereinthe bottommost die has a plurality of front side lands facing thesubstrate and a plurality of backside lands facing the next bottommostdie with a plurality of through silicon vias (TSVs) electricallycoupling the backside lands and the front side lands of the bottommostdie, wherein the next bottommost die has a plurality of front side landsfacing the bottommost die, wherein the plurality of backside lands ofthe bottommost die is directly coupled to the plurality of front sidelands of the next bottommost die by a solder layer, and wherein theplurality of front side lands of the bottommost die electrically couplesthe bottommost die to the substrate, wherein the TSVs of the bottommostdie are in direct contact with the backside lands of the bottommost diebut are not in direct contact with the front side lands of thebottommost die; an underfill material layer between the bottommost dieand the next bottommost die; and an encapsulation material over thesubstrate and laterally adjacent to the bottommost die, the nextbottommost die and the underfill material layer, wherein theencapsulation material is separate and distinct from the underfillmaterial layer.